The project VE-HEP will show the feasibility of using open-source tools in a wide range of the digital chip design value chain. This includes the use of an open-source processor design, the use of open-source design tools e.g. for the synthesis or the ”place and route”, as well as the development of public available automatic implementation schemes to harden the chip design against hardware attacks. The use case to implement all this ambitious goals is the design and fabrication of an open-source hardware security module (HSM) that will be integrated into an automotive application. To improve the quality and trustworthiness of such a critical module, verification schemes for the different design steps will be developed, extended and integrated into the design flow. 

Presentations, Papers, Flyer

Documents from 2023


Documents from 2022 

Requirements Analysis

In the first project phase we worked out the requirements for an open source tool chain to be demonstrated on a hardware security module. The full requirements report can be downloaded here. In its introduction our motivation is described [Requirements Report]

ASIC Design

  • FPGA
    an FPGA based rapid prototyping platform was developed to shorten the ASIC design time and increase the ASIC quality. The FPGA code can be found on our GitHUb
  • Processor
    GDS publication planned


Information about the Demonstrator will follow shortly. But it is already alive!

Hardening the value chain through open source EDA tools and Processors