Project

 What’s new in SIGN-HEP 

  • Industrialization focus: upgrade the open design flow into a repeatable, production-minded path for security ICs.
  • Hardening & verification at scale: expand side-channel/fault-injection countermeasures and formal checks for real-world robustness.
  • Reference designs & demos: deliver an open, industry-aligned HSM/Root-of-Trust reference with clear bring-up guides.
  • PDK & MPW continuity: keep leveraging accessible PDKs and shuttle runs to lower the barrier for replication.
  • Community & training: docs, tutorials, and hands-on material to help teams reproduce and extend our work.

Built on VE-HEP outcomes

  • Silicon-proven baseline: two tapeouts and a working demonstrator established the foundation. → See VE-HEP results
  • Open assets: RTL, firmware, and flow instructions remain public and actively maintained.
  • Transparent methods: open-source EDA + reproducible steps stay at the core of our approach.

Why it matters

Trust in hardware starts with transparency. SIGN-HEP turns transparent methods into deployable building blocks—so research teams, SMEs, and integrators can evaluate, reproduce, and adopt trustworthy silicon with fewer hurdles.

Presentations, Papers, Flyer, Links

Documents from 2025


Documents from 2024


Documents from 2023

 

Documents from 2022 


Requirements Analysis

In the first project phase we worked out the requirements for an open source tool chain to be demonstrated on a hardware security module. The full requirements report can be downloaded here. In its introduction our motivation is described [Requirements Report]


ASIC Design

  • FPGA
    an FPGA based rapid prototyping platform was developed to shorten the ASIC design time and increase the ASIC quality. The FPGA code can be found on our GitHUb 
    https://github.com/VE-HEP/VE-HEP-HW-SW
  • Processor
    GDS publication planned


Demonstrator

Information about the Demonstrator will follow shortly. But it is already alive!


HEP-Alliance
Open Source Silicon Pioneers Since 2020